The present invention relates to the manufacture of semiconductor-based devices. More particularly, the present invention relates to techniques for improving the etching of layers underlying a photoresist mask during manufacturing.
During the manufacture of semiconductor-based devices, i.e., electronic devices employing a semiconductor material, various layers may be deposited on a substrate and selectively etched to form the desired devices. To selectively etch a given layer, a photoresist mask is typically employed.
To facilitate discussion, FIG. 1 illustrates an exemplary layer stack 100, including a plurality of layers disposed on a substrate 102. Substrate 102 may take the form of, for example, a wafer or a glass panel, out of which integrated circuits or flat panel displays may be fabricated. The exemplary layer stack shown in FIG. 1 includes an oxide (SiO.sub.2) layer 104 disposed above substrate 102. Oxide layer 104 is typically formed using a suitable oxide formation process such as thermal oxidation (e.g., either wet or dry oxidation). A nitride (Si.sub.x N.sub.y such as Si.sub.3 N.sub.4) layer 106 is shown disposed above oxide layer 104 and is typically formed using a suitable nitride process such as low pressure chemical vapor deposition (LPCVD). Layer stack 100 may be employed to form, for example, the active area of an integrated circuit.
To facilitate the selective etching of nitride layer 106, a photoresist layer 108 is first deposited by, for example, a spin-on process. Thereafter, a conventional photolithography process is employed to pattern photoresist layer 108 to form a mask to facilitate etching of selective regions in nitride layer 106. By way of example, one such technique involves the patterning of photoresist layer 108 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. The photoresist mask formed is depicted in FIG. 2. Thereafter, areas of the photoresist-underlying layer that is unprotected by the mask (e.g., areas 202 and 204 of nitride layer 106) are then etched away, leaving behind the desired features.
As the density of electronic devices increases, the accuracy of the etching process becomes more critical. This is because when devices are packed closely together, the etch profile must be carefully controlled to prevent, for example, inadvertent electrical shorts among adjacent features. When the device size reaches the submicron ranges, e.g., 0.25 micron or below, it has been observed that conventional photoresist masks, at times, cause difficulties in the subsequent etch process.
To facilitate discussion of the problems encountered when the prior art photoresist mask is employed, without modification, to etch the photoresist-underlying layer (e.g., nitride layer 106), FIG. 3 illustrates a portion of nitride layer 106 of FIG. 2 after etching. In FIG. 3, there is shown a photoresist feature 108(a), representing for example one of the photoresist features of FIG. 2. A nitride feature 106(a) is also shown, representing the nitride material remaining after the nitride etch step.
As shown in FIG. 3, photoresist feature 108(a) exhibits a tapered profile, i.e., the angle formed by the vertical photoresist sidewall with the substrate plane is less than perpendicular. The tapered profile of the photoresist feature, which may be due to the photolithography step that patterns photoresist layer 108 and/or the isotropic component of the subsequent nitride etch, propagates downward through the nitride layer as the nitride etch proceeds. Accordingly, nitride feature 106(a) also assumes a tapered profile, with the dimension at the bottom of the nitride feature (122) being somewhat wider than that at the top (124).
The tapered profile of nitride feature 106(a) represents relatively poor control of the profile of the etched feature. The lack of profile control renders it difficult to control the critical dimension (CD) of the resultant nitride features. If the lack of profile control and/or CD control is particularly severe, the resultant etch features may be unsuitable for use in fabricating modern high density (e.g., submicron or below) devices.
It has been suggested that the etch profile may be improved by increasing the ion bombardment, or physical etch, component of the nitride etch. In a parallel plate plasma system, increasing ion bombardment may be accomplished by, for example, increasing the RF power setting, decreasing the etch pressure, reducing the gap between the parallel plates of the plasma processing chamber (or any combination of the above). While increasing ion bombardment may result in a more vertical etch sidewall, such an approach also has its drawbacks.
By way of example, ion bombardment, being a physical process, is not particularly selective among the different layers. Accordingly, it tends to indiscriminately etch all layers, including layers through which etching is undesired. Further, it is relatively difficult to precisely control the ion bombardment process. Accordingly, increasing the ion bombardment component of the etch may cause unintended damage to other layers and/or other features of the substrate. With reference to FIG. 4, for example, increasing the ion bombardment component may undesirably cause damage to underlying oxide layer 104 (in region 402) and/or substrate 102 (in region 404).
In view of the foregoing, there are desired techniques for improving the etch of layers underlying a photoresist layer during the manufacture of semiconductor-based devices.